II.1Processor microcircuits (microprocessor microcircuits, microcomputer microcircuits and microcontroller microcircuits) having a processing speed of 5 GFLOPS or more and an arithmetic logic unit (ALU) with an access width of 32 bit or more.

Integrated circuits having one or more electronic processing units with a “Total Processing Performance (TPP)” exceeding 6000. Note: 1. “Total Processing Performance (TPP)” is the aggregate over all electronic processing units on the integrated circuit of 2 x MacTOPS x the bit length of the operation. a. “MacTOPS” is the theoretical peak number of Tera (1012) multiply–accumulate operations (D=A×B+C) per second that the device can perform. b. The 2 in the formula is based on the industry convention of counting one multiply–accumulate operation D=A×B+C as 2 separate operations for datasheet reporting purposes. Therefore 2 x MacTOPS may correspond to the TOPS or FLOPS reported on a datasheet. The bit length of the operation is the largest bit length of the inputs to the multiply operation. Aggregate the ‘TPP’ for each processing unit on the integrated circuit to arrive at a total. ‘TPP’ = TPP1 + TPP2 +....+ TPPn (where n is the number of processing units on the integrated circuit). The rate of 'MacTOPS' is to be calculated at its maximum value theoretically possible. The rate of 'MacTOPS' is assumed to be the highest value the manufacturer claims in a manual or brochure for the integrated circuit. For example, the 'TPP' threshold of 6 000 can be met with 750 tera FLOPS (or 2 × 375 ‘MacTOPS’) at 8 bits or 300 tera FLOPS (or 2 × 150 ‘MacTOPS’) at 16 bits. If the electronic processing unit is designed for MAC computation with multiple bit lengths achieving different 'TPP' values, the highest TPP value shall be used.